Due to inaccuracies involved in processes used to fabricate integrated circuits (ICs), particularly analog ICs, certain circuit components of an IC must be tuned (i.e., “trimmed”) in order to achieve a desired performance or functionality. For example, termination impedances between the inputs and outputs (I/Os) of two ICs (or “chips”) on a printed circuit board (PCB) are often trimmed to reduce signal reflections and maintain signal integrity.
In high-speed I/O circuits, impedance matching of the links and buses between chips on a PCB is particularly important. As shown in FIG. 1, a typical high-speed link 100 on a PCB consists of a transmitter 102, a transmission line 104 and a receiver 104. The transmission line in a typical application comprises several sections (see FIG. 2): metallization 202 on the transmitter chip itself, bond wire 204 that connects the chip to a package leadframe; an electrical connection 206 between the leadframe and the PCB; a wire trace 208 that connects the package leadframe to a backplane; and corresponding sections from the backplane to the receiver chip 210.
In some applications, impedance mismatches between adjacent sections can be minimized by adding off-chip termination resistors at the transmitter side, the receiver side, or both. These off-chip termination resistors match the output and input impedances of the transmitter and receiver chips to the transmission line impedance. FIGS. 3A-C show various examples of how off-chip resistors may be utilized to minimize impedance mismatches. In particular, FIG. 3A shows a receiver side termination using a single parallel resistor 106. FIG. 3B shows a receiver side termination using a Thévenin resistor pair 107 and 108. And, FIG. 3C shows a transmitter side termination with a serial resistor 108.
While the simple solution of inserting off-chip resistors to minimize impedance mismatches can be effective in some low-frequency applications, it is not a viable solution for high-speed applications. In high-speed applications, the termination resistors must be placed as close as possible to the chips. This is not an easy task. Indeed, in complex ICs having a large number of closely spaced I/Os, placement of the termination resistors cannot even be performed at all.
To avoid the problems associated with placement of off-chip resistors, on-chip termination resistors may alternatively be used. On-chip resistors can offer a better impedance matching solution, since they are on-chip and, therefore, can be located closer to the transmitter and receiver than can off-chip resistors. However, the on-chip resistors that are traditionally used—unsilicided polysilicon resistors or n-well resistors—have various disadvantages. First, their resistance values vary substantially over typical voltage and temperature operating ranges. Second, they require substantial chip area to implement. Third, additional process steps and additional masks are required to manufacture the on-chip resistors. Finally, the on-chip resistors cannot be adjusted once they are formed. This limitation can make it difficult to provide an accurate impedance match and does not allow the resistor to be adjusted at a later time.
One way to make termination resistors adjustable is to use transistor or resistor arrays in combination with a comparator circuit. This approach is shown in FIG. 4A. The adjustable impedance matching apparatus 400 includes a group 402 of parallel transistors, a comparator 404 having a resistor divider (first and second resistors 406 and 408), which is coupled to the comparator's non-inverting input, an external reference resistor 410 (RRef), which is coupled to the inverting input of the comparator, and an impedance element control block 412 coupled between the group of parallel transistors 402 and the output of the comparator 404.
The comparator 404 compares the voltage at its inverting input to the voltage at the common node of the resistor divider. Depending on the comparator output, the impedance control block 412 either turns ON or turns OFF one or more of the transistors in the group of parallel transistors 402 until the voltages at the inputs of the comparator 404 are the same. The desired impedance of the group of parallel transistors 402 can be determined, therefore, by proper selection of the ratio of the first and second resistors 406 and 408 and the reference resistor 410.
One problem with the adjustable impedance matching apparatus in FIG. 4A is that the resistances provided by the transistors can be nonlinear. To reduce the effect of the nonlinear transistor resistances, a resistor 414 may be added in series with the group of parallel transistors 402, as shown in FIG. 4B. However, these added resistors are usually unsilicided polysilicon resistors and, undesirably, take up the same amount of chip area, require the same additional process steps, and provide the same unacceptably large variations in resistance as do the on-chip termination resistors described above. In addition to these problems, the array of resistors and transistors undesirably occupies area on the chip which would otherwise be available for other circuitry. Addition of the transistors and resistors also complicates the semiconductor fabrication processes.
Given the foregoing problems and limitations of prior art impedance matching approaches, it would be desirable to have impedance matching and trimming methods and apparatuses that: provides precise resistance values over the range of IC process variation, operating temperature, operating voltage, and operating life; uses a minimum of IC surface area; and does not require introduction of an excess number of steps in the IC fabrication and assembly process.